1. Field of the Invention
The present invention relates to a method of forming asymmetric source/drain for a DRAM cell and more particularly to a method of forming transistors with reduced short channel effect (SCE) and junction leakage current so as to improve the reliability of a DRAM device.
2. Description of the Prior Art
As the function of a microprocessor is becoming more and more powerful and the operation scale of computer programs software is becoming larger and larger, the demand for increasing the memory capacity of a memory storage device increases substantially. Strong demand for high capacity memory storage have provided a driving force pushing the semiconductor manufacturing technology to a higher level of integration, which aims at fabricating low-cost memory devices with high memory capacity. Attributed to 1T1C (1-Transistor, 1-Capacitor) structure adopted by DRAM cell higher integration level in comparison with other types of memory devices can be realized. The size of a transistor in a DRAM cell is therefore shrunk in order to increase the level of integration in a DRAM device. However, as the size is reduced to a sub-micron level, short channel effect (SCE) and junction leakage current become very serious problems.
When the problem of a junction leakage current occurs, the charges stored in the capacitor of a DRAM can leak, which then leads to an aggravated decaying of the sensing signal during each refresh cycle. Although by raising the frequency of the refresh cycle the above-mentioned problem can be resolved; however, the operation of raising the frequency of the refresh cycle by itself can seriously and adversely affect the performance of the entire system.
Conventionally, one of the methods used to solve above-mentioned problems is the method of forming symmetrically graded junctions in the substrate on opposite sides of the gate electrode to suppress the junction leakage, which subsequently improves the cell charge retention. However, this method tends to exacerbate the short channel effect. Another method forms symmetric abrupt junctions in the substrate on opposite sides of the gate electrode to suppress the short channel effect. However, this second method tends to dramatically worsen the junction leakage problem, especially the gate-induced-drain-leakage (GIDL), which subsequently exacerbate the leakage of the stored charges.